Memory reliability, availability and serviceability (RAS) features have been traditionally performed and/or managed at a system level by a central processing unit (CPU) and/or memory controller (MC). In some configurations, a CPU and a MC are separate components of a host system. In other configurations, the CPU and the MC are integral. As used herein, the acronym CPU/MC means a CPU and/or an MC. For example, a CPU/MC has traditionally sent a refresh command to dynamic random access memory (DRAM) of a system memory to initiate refresh of the DRAM. Error correction using an error correcting code (ECC) has also been traditionally performed by a CPU/MC reading individual memory locations, correcting data using the ECC and the rewriting the data. Another RAS feature that has been traditionally performed by a CPU/MC is “scrubbing” of the system memory in which the CPU/MC periodically reads regions of a system memory, corrects errors (using ECC) and writes corrected data back to the region of the system memory. Yet another RAS feature that has been traditionally performed by a CPU/MC is wear-leveling management in which a CPU/MC remaps memory pages of a non-volatile memory using, for example, a write-count table and a remap table to swap memory pages using read and write commands to balance wear in the non-volatile memory.